Design Logic Online

Mastering the Verilog case Statement: Syntax, Examples, and Best Practices

制御構文と条件分岐
佐川 直弘 | Naohiro Sagawa
By 佐川 直弘 | Naohiro Sagawa (運営者)
※記事内に広告を含みます。Amazonアソシエイトとして適格販売により収入を得ています。
目次

1. Introduction

Verilog is one of the Hardware Description Languages (HDL) widely used for digital circuit design. Among its features, the case statement is an essential construct for efficiently describing conditional branching. It is especially common in the design of state machines (FSMs) and multiplexers. In this article, we will cover the basics, advanced use cases, and best practices for Verilog’s case statement. With practical code examples explained step by step, even beginners can follow along easily, so be sure to read until the end.

2. Basic Syntax of the Verilog case Statement

What is a case Statement?

The Verilog case statement is a construct that executes different operations based on a given condition (selector). It works similarly to the switch-case statement in C, but with some key differences. The basic syntax is as follows:
case (expression)
    condition1: statement1;
    condition2: statement2;
    condition3: statement3;
    default: statement4;  // Executes if no condition matches
endcase

Basic Usage of case

The following example shows a simple case statement that assigns different signals to out depending on the 2-bit input sel:
module case_example(input [1:0] sel, output reg [3:0] out);
    always @(*) begin
        case (sel)
            2'b00: out = 4'b0001;
            2'b01: out = 4'b0010;
            2'b10: out = 4'b0100;
            2'b11: out = 4'b1000;
            default: out = 4'b0000;  // Default value for safety
        endcase
    end
endmodule
Here, out takes different values depending on sel. By including the default case, unexpected inputs are handled safely.

Differences Between case, casex, and casez

Verilog provides extended forms of case: casex and casez. These work like wildcards, allowing certain bits to be ignored.
SyntaxCharacteristics
caseRequires an exact match (default behavior)
casexIgnores X (unknown) and Z (high impedance) values
casezIgnores only Z values
Example using casez:
casez (sel)
    2'b1?: out = 4'b1111; // Matches if the MSB is 1
    2'b01: out = 4'b0001;
    default: out = 4'b0000;
endcase
Here, 1? means that as long as the most significant bit is 1, it matches regardless of the lower bit.

3. Practical Examples of case

Basic Conditional Branching

The following example shows a simple CPU decoder that executes different operations depending on the value of an 8-bit opcode:
module decoder(input [7:0] opcode, output reg [3:0] control_signal);
    always @(*) begin
        case (opcode)
            8'h00: control_signal = 4'b0001; // NOP
            8'h01: control_signal = 4'b0010; // ADD
            8'h02: control_signal = 4'b0100; // SUB
            default: control_signal = 4'b0000; // Undefined instruction
        endcase
    end
endmodule

Using case in State Machines

The case statement is widely used in FSMs (Finite State Machines):
typedef enum reg [1:0] {IDLE, RUN, STOP} state_t;
state_t current_state, next_state;

always @(posedge clk) begin
    if (reset)
        current_state <= IDLE;
    else
        current_state <= next_state;
end

always @(*) begin
    case (current_state)
        IDLE: next_state = RUN;
        RUN:  next_state = STOP;
        STOP: next_state = IDLE;
        default: next_state = IDLE;
    endcase
end
This implements a 3-state FSM. For circuits that require state management, case makes the logic much clearer.

4. Best Practices and Caveats

When using the case statement in Verilog, keep the following points in mind:

1. Always Include a default Case

It’s important to cover all possible inputs. In FPGA or ASIC synthesis, omitting default can cause unintended latch generation.

2. Use casex and casez with Caution

These constructs can match unintended signals. Always simulate thoroughly when using them.
casez (sel)
    2'b1?: out = 4'b1111; // Matches if MSB = 1
    2'b01: out = 4'b0001;
    default: out = 4'b0000;
endcase

3. Don’t Overuse case

For small conditional branches, if-else can be more intuitive and readable. Use case mainly when there are multiple options to handle.

5. Conclusion

In this article, we covered the following about the Verilog case statement: ✅ Basic syntax and behavior ✅ Differences between case, casex, and casez ✅ Practical usage (conditional branching, FSMs) ✅ Key caveats and best practices By using the case statement properly in Verilog, you can improve readability and prevent design errors. Apply these concepts in your future designs!

What to Learn Next in Verilog

Once you understand the case statement, the next step is to study the always block and the difference between combinational and sequential circuits for deeper insights into Verilog design.