The Comprehensive Guide to Verilog HDL: From Basics to Practical Design

By 佐川 直弘 | Naohiro Sagawa (運営者)

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1. What is Verilog? Overview and Applications

Basic Definition of Verilog

Verilog is one of the Hardware Description Languages (HDL) used for designing digital circuits. While software programming languages are used to write computer programs, Verilog is used to describe the behavior of digital circuits and systems. Using this language simplifies complex circuit design and allows designers to efficiently perform simulations and synthesis (conversion of the circuit into a manufacturable form).

Verilog was developed in 1984 and standardized by the IEEE (Institute of Electrical and Electronics Engineers) in 1995. It has continued to evolve and is now widely used for designing FPGAs (Field-Programmable Gate Arrays) and ASICs (Application-Specific Integrated Circuits).

Role of Verilog in Digital Circuit Design

Digital circuit design is the process of building systems that process information using electrical signals. Examples include the processors and memory that operate inside smartphones and computers. Verilog is utilized as a tool to streamline the design of such digital systems.

Specifically, it is used in the following situations:

• FPGA Design: FPGAs are devices with high circuit design flexibility. Using Verilog, you can freely define the functions of an FPGA and utilize it as a reprogrammable device.
• ASIC Design: ASICs are integrated circuits specialized for specific purposes. Verilog enables the design of custom ICs.
• Simulation: Circuits described in Verilog can be simulated in software to verify their operation beforehand. This allows for early detection and correction of design errors.

What You Will Learn in This Article and Target Audience

In this article, we will explain the following topics step-by-step for those who are new to Verilog or want to review the basics:

1. Basic Verilog syntax and design fundamentals
2. Practical design examples and debugging methods
3. Introduction to helpful learning resources and tools

The target audience includes:

• Beginners who want to learn Verilog or HDL
• Engineers who are about to start designing FPGAs or ASICs
• Designers or students who want to review their basic knowledge

2. Basic Verilog Syntax and Concepts

Basic Verilog Syntax and Mechanism

Definition and Usage of Modules

When starting a design in Verilog, the most basic unit is a “module.” A module represents a component of a circuit and is where inputs, outputs, and internal structure are described. Below is an example of a simple module:

module AND_gate (
    input wire a, // 入力a
    input wire b, // 入力b
    output wire y // 出力y
);
    assign y = a & b; // AND演算
endmodule

This code describes a circuit that performs an AND operation on two input signals (a and b) and connects the result to the output (y). A module is defined with the keyword module and terminated with endmodule.

Types of Data Types and Selection (Distinction between wire and reg)

There are mainly two types of data types in Verilog:

• wire: Represents a wire. It is used to connect signals.
• reg: Represents a register. It is used to hold values synchronized with a clock.

For example, the following code uses wire and reg differently:

module Example (
    input wire clk,    // クロック入力
    input wire rst,    // リセット入力
    input wire a,      // 入力a
    output reg y       // 出力y
);
    always @(posedge clk or posedge rst) begin
        if (rst)
            y <= 0;    // リセット時、出力を0に
        else
            y <= a;    // クロック時、入力aを出力yに代入
    end
endmodule

Here, the output y changes according to the clock signal clk. The reg type is used to hold values and is utilized within an always block.

Control Structures (if, case) and Notes on Simulation

How to Use if Statements

In Verilog, the if statement is used to describe conditional branching. Below is a basic example of an if statement:

always @(posedge clk) begin
    if (a == 1'b1)
        y <= 1'b0;  // aが1の場合、yを0に設定
    else
        y <= 1'b1;  // それ以外の場合、yを1に設定
end

The if statement is useful for changing the circuit’s behavior based on conditions.

How to Use case Statements

When you want to branch based on multiple conditions, using a case statement is more efficient. Below is an example representing state transition:

always @(state) begin
    case (state)
        2'b00: y = 1'b0;
        2'b01: y = 1'b1;
        2'b10: y = 1'b0;
        2'b11: y = 1'b1;
        default: y = 1'bx; // 不明な状態
    endcase
end

In this example, the output y changes depending on the state state. Using a case statement makes the code more readable.

Fundamental Concepts Beginners Should Know

Difference between Blocking and Non-blocking Assignments

In Verilog, there are two main types of assignment methods:

• Blocking Assignment (=): A series of processes are executed sequentially.
• Non-blocking Assignment (<=): Values are updated in parallel.

Let’s look at an example:

always @(posedge clk) begin
    a = b;     // ブロッキング代入
    c <= d;    // ノンブロッキング代入
end

Blocking assignment behaves like software where instructions are executed sequentially. On the other hand, non-blocking assignment is used to accurately describe hardware that operates in parallel. It is generally recommended to use non-blocking assignment (<=) within always blocks.

Concept and Description Method of Parallel Processing

Verilog supports the description of hardware capable of parallel processing. In the following example, two always blocks operate independently:

always @(posedge clk) begin
    a <= b + 1;
end

always @(posedge clk) begin
    c <= d - 1;
end

In this way, independent processes are executed for each always block, allowing for the description of behavior close to actual hardware circuits.

Difference between Simulation and Synthesis

• Simulation: The process of verifying whether the designed circuit operates as expected in software.
• Synthesis: The process of converting the design into actual hardware.

In Verilog, code written for simulation (e.g., initial blocks) is not used for synthesis. Therefore, it is important to clearly separate synthesizable code from simulation-only code.

3. Key Features and Characteristics of Verilog

Characteristics of Verilog and Differences from Other HDLs

Strengths of Verilog

Verilog has the following strengths compared to other Hardware Description Languages (HDLs):

1. Simple Syntax

• Verilog has a syntax similar to C language, making it easy for engineers with programming experience to learn.
• Basic syntax like modules, data types, and operators is intuitive, making it a beginner-friendly design.

1. Extensive Support

• Verilog is standardly supported by FPGA and ASIC design tools (e.g., Vivado, ModelSim).
• The existence of abundant learning resources and communities supports beginners’ learning.

1. Highly Flexible Design Methodology

• It supports a wide range of design methodologies, from low-level to high-level, centering on RTL (Register Transfer Level) design.

Comparison with VHDL and SystemVerilog

Let’s look at how Verilog differs compared to other HDLs, especially VHDL and SystemVerilog.

• Difference from VHDL: VHDL has strict syntax which helps prevent errors, but Verilog is efficient in that it is simpler and requires less code.
• Difference from SystemVerilog: SystemVerilog is a superset of Verilog and adds advanced verification features and object-oriented programming capabilities.

When beginners start digital design, Verilog is generally chosen due to its concise syntax.

Specific Use Cases of Verilog

Role of Verilog in FPGA Design

FPGAs are user-programmable integrated circuits. Using Verilog allows for easy design of complex logic circuits. Here is the role of Verilog in FPGA design:

1. Prototyping

• Used to verify circuit operation during the early stages of product development.
• Rapid prototyping can be done using Verilog, allowing for flexible response to specification changes.

1. Behavioral Verification

• In FPGA design, simulation is performed using Verilog to detect design errors early.
• Testbenches are created using simulation tools (e.g., ModelSim) to verify the circuit’s behavior.

Circuit Simulation Flow

The basic flow of simulation using Verilog is as follows:

1. Circuit Description

• Describe the circuit to be designed using Verilog.

1. Testbench Creation

• A testbench defines the environment for verifying the behavior of the designed circuit. Below is an example of a simple testbench:

module Testbench;
    reg a, b;
    wire y;

    // テスト対象のモジュールをインスタンス化
    AND_gate uut (
        .a(a),
        .b(b),
        .y(y)
    );

    initial begin
        // テストパターンの適用
        a = 0; b = 0;
        #10; a = 0; b = 1;
        #10; a = 1; b = 0;
        #10; a = 1; b = 1;
        #10;
    end
endmodule

3. Simulation Execution

• Run the testbench with a simulator and check if the circuit’s behavior is as expected.

3. Result Analysis

• Analyze the simulation output to identify design issues.

4. Practical Design Examples Using Verilog

Learning with Verilog Sample Code

Counter Design Example (with Code Explanation)

A counter is a fundamental and important element in digital circuit design. Below is an example of a counter that increments its value based on a clock signal:

module Counter (
    input wire clk,    // クロック入力
    input wire rst,    // リセット入力
    output reg [3:0] count // 4ビットのカウンタ出力
);
    always @(posedge clk or posedge rst) begin
        if (rst)
            count <= 4'b0000; // リセット時にカウンタを0にする
        else
            count <= count + 1; // クロックが立ち上がるたびにカウンタをインクリメント
    end
endmodule

Explanation:

1. clk is the clock signal, which controls the timing of the circuit.
2. rst is the reset signal, which initializes the counter.
3. The counter value is represented by 4 bits (0-15) and increments synchronized with the rising edge of the clock signal.

Description and Application Examples of Finite State Machines (FSM)

FSM (Finite State Machine) is used when designing circuits with multiple states. Below is an example of an FSM design with three states:

module FSM (
    input wire clk,    // クロック入力
    input wire rst,    // リセット入力
    input wire in,     // 状態遷移のトリガー
    output reg [1:0] state // 現在の状態
);
    // 状態定義
    localparam STATE0 = 2'b00,
               STATE1 = 2'b01,
               STATE2 = 2'b10;

    always @(posedge clk or posedge rst) begin
        if (rst)
            state <= STATE0; // 初期状態
        else begin
            case (state)
                STATE0: state <= (in) ? STATE1 : STATE0;
                STATE1: state <= (in) ? STATE2 : STATE0;
                STATE2: state <= (in) ? STATE0 : STATE1;
                default: state <= STATE0;
            endcase
        end
    end
endmodule

Explanation:

1. States are defined using localparam.
2. State transitions are performed based on the input in using a case statement.
3. This design example can be applied to, for example, simple control systems or signal generation circuits.

Designing a Simple Adder (Steps for Beginners)

Next, let’s design a simple 2-bit adder:

module Adder (
    input wire [1:0] a, // 2ビットの入力a
    input wire [1:0] b, // 2ビットの入力b
    output wire [2:0] sum // 3ビットの出力（最大値が3ビットになるため）
);
    assign sum = a + b; // 加算処理
endmodule

Explanation:

1. Addition is performed using the assign statement.
2. The output is set to 3 bits to account for carry-over.
3. Such adders are important as a foundation for arithmetic processing circuits.

Common Challenges and Solutions

Common Error Examples (During Simulation and Synthesis)

1. Simulation Errors

• Error Example: Signal becomes undefined (x).
• Cause: Insufficient initialization or incorrect module connection.
• Solution: Clearly define input signals and initial states, or perform initialization in the testbench.

1. Synthesis Errors

• Error Example: Non-synthesizable syntax (e.g., initial block).
• Cause: Using descriptions not supported by the synthesis tool.
• Solution: Use synthesizable syntax (e.g., always block).

How to Utilize Debugging Tools

Debugging is very important when proceeding with design in Verilog. Below are commonly used debugging tools and their usage:

1. Simulator (e.g., ModelSim)

• By checking simulation results in waveforms, you can verify signal timing and behavior.

1. Waveform Viewer

• Visually check the changes in input and output signals to identify design issues.

1. Debug Messages

• Use display statements to output debug information and check signal values and states:

   initial begin
       $display("Initial state: %b", state);
   end

5. Resources and Tools for Learning Verilog

Recommended Resources for Learning Verilog

Books and Online Tutorials for Beginners

For those learning Verilog for the first time, it’s important to use reliable learning materials. Below are resources recommended for beginners:

1. Books

• “Introduction to Digital Design with HDL”
  • A classic Japanese book where you can learn basic concepts of Verilog and VHDL while comparing them.
• “Verilog HDL: A Guide to Digital Design and Synthesis”
  • Although in English, it is an excellent book where you can systematically learn from basics to practical applications.
• “Digital Design and Verilog HDL Fundamentals”
  • A detailed explanation of digital circuit design in Verilog, aimed at beginners to intermediate learners.

1. Online Tutorials

• YouTube
  • Many tutorials are available for free in Japanese and English. The advantage is that you can learn while running actual code.
  • Examples: Video series such as “Verilog Introduction” and “Fundamentals of FPGA Design”.
• Websites
  • EDA Playground: An online environment where you can try out Verilog code in your browser.
  • ASIC World: You can learn everything from basic Verilog syntax to practical design examples.

Introduction to Video Courses and Practical Learning Materials

1. Udemy

• There are courses such as “Verilog for Beginners” and “Learning FPGA Design,” where you can learn with videos and hands-on exercises.
• Although there is a cost, the content is comprehensive for beginners to learn systematically.

1. Coursera

• Offers university-level online courses specializing in hardware design. You can learn from fundamentals to advanced design.

Tools to Support Development

Modeling Tools (ModelSim, Vivado, etc.)

1. ModelSim

• A classic tool for Verilog simulation. Used to check signal behavior and waveforms.
• Features
  • Easy-to-use interface for beginners.
  • Intuitive waveform viewer ideal for debugging.

1. Vivado

• An FPGA design tool provided by Xilinx, which supports design using Verilog.
• Features
  • Provides integrated support from RTL design to simulation, synthesis, and implementation.
  • Smooth integration with FPGA development boards (e.g., Zynq, Artix).

How to Choose and Introduce Synthesis Tools

1. Quartus Prime

• FPGA development tool from Intel. A free version is also available for beginners.
• Pros
  • Circuit diagrams can be visualized within the tool.
  • Easy integration with Cyclone series FPGAs.

1. ISE Design Suite

• A tool for older Xilinx FPGAs, suitable for use in educational institutions.
• Pros
  • Ideal for design using learning boards (e.g., Basys 2).

6. Verilog FAQ

How Should Beginners Learn Verilog?

Question: I’m just starting to learn Verilog, how should I proceed?

Answer:

1. Start from the Basics:

• Start with designing simple circuits (e.g., AND gate, OR gate). It is important to understand basic syntax and how to use modules.

1. Utilize Simulation Tools:

• Check the behavior of the code you wrote using tools like ModelSim or Vivado. Performing actual simulations will deepen your understanding.

1. Use Reliable Resources:

• We recommend using books and online tutorials to learn systematically (refer to “5. Resources and Tools for Learning Verilog”).

1. Challenge Yourself with Projects:

• Once you have learned the basics, work on simple projects (e.g., 4-bit counter or FSM) to gain practical skills.

VHDL vs. Verilog: Which Should You Choose?

Question: Which should I learn, VHDL or Verilog? When do you use each?

Answer:

1. Situations to Choose Verilog:

• With its simple syntax, Verilog is easier for beginners and those with C language experience to learn.
• It is widely used in prototyping and FPGA design.

1. Situations to Choose VHDL:

• Suitable for mission-critical systems and situations requiring large-scale and rigorous design.
• Its strict type checking and syntax are advantageous in preventing design errors.

1. Selection Criteria:

• Ease of Learning: Verilog is optimal for beginners.
• Project Requirements: Align with the language used in the project.
• Tool Support: Many tools support both languages, but choose the optimal language based on the design target (FPGA or ASIC).

Common Mistakes Beginners Should Avoid

Question: What are common mistakes beginners make while learning Verilog? How can they be prevented?

Answer:

1. Lack of Initialization:

• Signals often become x (undefined value) during simulation.
• Solution: Always set initial values or perform initialization in the testbench.

   initial begin
       signal = 0; // 信号を初期化
   end

2. Confusion between Blocking and Non-blocking Assignments:

• Confusing = (blocking assignment) and <= (non-blocking assignment) can lead to unexpected behavior.
• Solution: Use non-blocking assignment (<=) in clock-synchronous always blocks.

2. Confusing Synthesizable Code with Simulation Code:

• Including simulation-only descriptions (e.g., initial blocks) in synthesizable code will cause errors.
• Solution: Clearly separate synthesizable code from simulation-only code.

2. Lack of Understanding of Parallel Processing:

• Since Verilog describes circuits that operate in parallel, it is easy to confuse it with sequential processing like in software.
• Solution: Learn the basic concepts of parallel processing and be aware that multiple always blocks operate independently.

7. Learning Verilog and Taking the Next Steps

Reviewing Verilog Learning and Preparing for the Next Steps

Review

• Understanding Basic Syntax: Confirm that you can describe modules, data types, and control structures.
• Mastering Practical Examples: It’s important that you can build basic digital circuits through the design of counters and FSMs.
• Tool Utilization: Ensure you have mastered basic simulation and debugging operations using tools like ModelSim and Vivado.

Preparation for the Next Steps

• If you understand the basics at this point, you are ready to move on to advanced topics.
• Follow the steps below to acquire new skills and knowledge.

Moving on to FPGA Design

Learn the Fundamentals of FPGA

FPGA (Field-Programmable Gate Array) is an optimal platform for applying your Verilog skills. FPGAs are programmable hardware and can accommodate various designs.

1. Prepare an FPGA Development Board

• Boards for Beginners: We recommend Digilent’s Basys 3 or Nexys A7.
• Reason: There are abundant learning materials, and they integrate easily with tools like Vivado.

1. Challenge Simple Projects

• Start with simple projects like LED blinking or switch control.
• Learn the basics of FPGA design through clock division circuits and controlling multiple inputs.

1. Challenge Complex Systems

• Work on designing control systems integrating multiple FSMs and memory interfaces to expand your skills.

Transitioning to SystemVerilog

Reasons to Learn SystemVerilog

• SystemVerilog is designed as an extension of Verilog and allows for advanced verification features and object-oriented descriptions.
• It is particularly powerful in creating testbenches and designing large-scale systems.

Topics to Learn

1. Class-Based Testbenches

• Using SystemVerilog enables random testing and coverage analysis.

1. Utilizing Interfaces

• Allows for concise description of complex inter-module communication.

1. Extended Control Structures

• Learn features that enhance design safety, such as the unique and priority keywords.

Working on Real Projects

Participate in Open Source Projects

You can gain practical experience by participating in open source digital design projects available on platforms like GitHub. For example:

• RISC-V Processor Design
• Simple DSP (Digital Signal Processing) Modules

Start an Original Project

• Try creating original digital designs in areas you are interested in.
• Examples: Digital clock, audio processor, signal filtering circuit, etc.

Suggestions for the Next Learning Steps

Acquiring Advanced Design Skills

1. Pipeline Design

• Learn the fundamentals of pipeline design used in high-speed processors and signal processing circuits.

1. Understanding Clock Domains

• Learn how to properly transfer signals between modules with different clock speeds.

1. Low-Power Design

• Acquire more practical skills by incorporating design techniques that prioritize power efficiency.